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WLAN Application을 위한 CMOS 송수신기와 OFDM 모뎀의 연구

A Study of CMOS Transceiver and OFDM Modem for 2.4GHz WLAN Application

  • 김신웅 (Shin-Woong Kim, 한동대학교 대학원)

초록/요약

본 석사학위 논문은 802.11 a/g WLAN application을 위한 CMOS 무선 송수신기 와 OFDM MODEM의 설계 및 연구에 대한 내용을 다루게 된다. 무선송수신기는 중간 주파수를 사용하지 않는 직접 변환 방식의 송수신기로 ADC(Analog to Digital Convertor), DAC(Digital to Analog Convertor), LPF(Low-pass Filter), VGA(Variable-gain Amplifier), Mixer, LNA(Low-noise Amplifier), PA(Power Amplifier), 그리고 PLL(Phase Locked Loop)의 block으로 구성이 된다. 설계는 1P6M 0.18um CMOS(Thick gate지원) 공정을 이용하였다. OFDM MODEM은 무선랜 표준인 IEEE 802.11 a/g 방식을 지원하며 1P6M 0.18um CMOS공정을 통해 합성 및 라우팅을 수행하였다. FPGA를 이용하여 검증 하였으며, 무선 송수신기를 제외한 모뎀 부분의 검증 결과 BPSK, QPSK, 16-QAM, 64-QAM 등에서 안정적인 동작을 하였다. 송신기를 구성하는 DAC는 10bit 온도계디코더방식의 DAC 구조 이고, 1Vpp의 Dynamic range를 가진다. LPF는 cut-off 주파수를 2.7MHz에서 17MHz까지 가변할 수 있으며 VGA는 구현하기 쉽고 간단한 Weighted-sum 구조로, -10.5dB ~ 15.7dB의 가변 이득을 갖도록 설계하였다. 그리고 Gain을 낼 수 있는 gilbert-cell 구조의 Active Mixer를 설계하여, PA가 최대 0 dBm의 출력 파워를 내는데 어려움이 없도록 하였다. 마지막으로 낮은 전력에서 구동하는 Cascode 구조의 10dB의 power gain을 가지는 Drive Ampilfier를 구현하였다. 수신기는 Pipe line ADC, VGA, LPF, Active Down Mixer, 그리고 LNA로 구성되어 있으며, ADC는 40MHz의 고속에서도 동작하며, 입력 Dynamic range는 1Vpp로 설계되었다. VGA와 LPF는 송신기와 같은 구조를 사용하였으며, Mixer는 Active mixer를 사용하여, 변환 이득을 가지도록 하였고, LNA는 Fully differential 구조로 잡음에 강하고, 15dB이상의 전력이득을 낼 수 있도록 설계하였다. 송수신 단의 Mixer에 Local 신호를 공급하기 위해 Integer-N 방식의 Phase Locked Loop 주파수 합성기가 설계 되었으며 I와 Q 신호를 공급하기 위해 Quadrature 신호의 출력이 가능한 VCO(Voltage Controlled Oscillator)가 사용되었다. 이 외에 주파수 합성기를 구성하는 block으로 8/9 Dual Modulus Prescaler, CP(Charge Pump), PFD(Phase Frequency Detector)를 설계하였으며 추가적으로 R-C와 charge pumping, register를 이용한 Prescaler를 제안하였다.

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초록/요약

This master thesis will cover the design and study of CMOS wireless transceiver and OFDM modem for 802.11a/g WLAN application. The transceiver is a direct conversion type which does net use the intermediate frequency and consists of ADC(Analog to Digital Convertor), DAC(Digital to Analog Convertor), LPF(Low-pass Filter), VGA(Variable-gain Amplifier), Mixer, LNA(Low-noise Amplifier), PA(Power Amplifier), and PLL(Phase Locked Loop). For design of the system, 1P6M 0.18um CMOS (Thick gate support) process was used. The OFDM modem supports IEEE 802.11a/g, standard of WLAN, and 1P6M 0.18um CMOS (Thick gate support) process was also used for synthesis and routing. The OFDM modem was verified using FPGA, and the stable operation was in BPSK, QPSK, 16-QAM, 64-QAM except for transceiver. The DAC, one of the blocks of transmitter, has thermometer decoder structure and 1Vpp dynamic range. The cut-off frequency of LPF could vary from 2.7MHz to 17MHz, the Weighted-sum type VGA was designed to have variable gain from -10.5dB to 15.7dB. The UP-mixer is double balanced active type. Because of the active mixer, it is not difficult for power amplifier driver to output the maximum power more than 0 dBm. Finally, the power amplifier driver has 10dB power gain and cascade structure. The receiver consists of the pipeline ADC, VGA, LPF, active down mixer, and LNA. The ADC operates at high speed of 40MHz, input dynamic range was design to be 1Vpp. The VGA and LPF have the same structure to transmitter’s one, and the mixer uses active type with conversion gain. The LNA designed as fully differential structure is resistant to noise and has power gain more than 15dB. The Integer-N phase locked loop was implemented to supply the local frequency to mixer. For I-Q complex signal, the Quadrature VCO was used. In other blocks of the PLL, 8/9 dual modulus prescaler, charge pump, phase frequency detector was designed. In addition, the prescaler using charge pumping and register was proposed.

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목차

Abstract 1
Contents 5
List of Figures 7
List of Tables 11
1. Introduction 12
2. The Architecture of Transceiver 13
2.1 The Architecture of Receiver 15
2.2 The Architecture of Transmitter 17
3. Design and Simulation of WLAN Transceiver 18
3.1 Receiver 18
3.1.1 LNA (Low Noise Amplifier 19
3.1.2 Down Mixer 26
3.1.3 LPF (Low Pass Filter) 31
3.1.4 VGA (Variable Gain Amplifier) 39
3.1.5 ADC (Analog to Digital Convertor) 42
3.2 Transmitter 46
3.2.1 Active Up-Mixer & Power Amplifier Driver 47
3.2.2 DAC (Digital to Analog Convertor) 52
4. Design and Simulation of PLL Frequency Synthesizer 56
4.1 VCO (Voltage Controlled Oscillator) 59
4.2 PFD (Phase Frequency Detector) 63
4.3 CP (Charge Pump) 65
4.4 Loop Filter 67
4.5 Prescaler 71
4.5.1 8/9 Prescaler 72
4.5.2 Prescaler based on Charge Pump 74
4.6 PLL Frequency Synthesizer Locking Simulation 78
5. Measurement 80
5.1. Verification Environment 80
5.2. Measurement result 83
5.2.1 VGA 83
5.2.2 Prescaler 85
5.2.3 ADC 89
5.2.4 DAC 90
6. OFDM Modem 92
6.1. Specification of IEEE 802.11a/g OFDM PHY 93
6.1.1 802.11a/g OFDM PHY Layer outline 94
6.1.2 PLCP frame format 95
6.1.3 PLCP preamble 97
6.1.4 Scrambler/Descrambler 98
6.1.5 Convolution Encoder 99
6.1.6 Interleaver/Deinterleaver 101
6.1.7 Sub carrier modulation mapping 102
6.1.8 Pilot subcarriers 105
6.2 Implementation of OFDM PHY 107
6.2.1 Power detection and automatic gain control 110
6.2.2 Synchronize 112
6.2.2.1 Symbol timing detection 112
6.2.2.2 Carrier frequency offset recovery 115
6.2.3 Fast Fourier Transform 118
6.2.4 Equalizer 126
6.2.5 Viterbi decoder 132
6.2.6 Modem Simulation result 136
7. Conclusion 142
8. Bibliography 143
9. Acknowledgement 145

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